DLink: RISC-V Debugger Firmware based on rvlink
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Jul 1, 2024 - C
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riscv-debug
Here are 3 public repositories matching this topic...
BLogic MCU - RISC-V (CV32E40P, RV32IMC) microcontroller SoC with a custom AXI4 interconnect and a TinyConv keyword-spotting AI accelerator (21× vs software). sky130 GDSII signed off at 27 MHz, runs on a Genesys 2 FPGA at 50 MHz, JTAG debug. TEKNOFEST 2026 Chip Design Competition - OSTİM Technical University
microcontroller asic fpga vivado systemverilog soc uvm keyword-spotting risc-v jtag verilator axi4 tinyml sky130 chipdesign riscv-debug cv32e40p ai-accelerator librelane teknofest2026
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Oct 6, 2026 - Verilog
Implementation of RISC-V CPU with external debug support via JTAG
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Feb 15, 2024 - TeX
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