Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

Name		Name	Last commit message	Last commit date
.github		.github
control		control
doc		doc
ghdl_vunit		ghdl_vunit
logging		logging
octave		octave
.btd.yml		.btd.yml
.gitignore		.gitignore
.gitpod.Dockerfile		.gitpod.Dockerfile
.gitpod.yml		.gitpod.yml
Bridging HW and SW verification with VUnit co-simulation.pdf		Bridging HW and SW verification with VUnit co-simulation.pdf
README.md		README.md

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