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1. npu-uvm-verificationNxN npu-uvm-verificationNxN Public

   Parameterized NxN systolic-array NPU for signed matrix multiplication, implemented in SystemVerilog RTL and verified using UVM, SVA, directed testing, formal verification, functional coverage, and …

   SystemVerilog 5

2. npu-uvm-verification2x2 npu-uvm-verification2x2 Public

   NPU 2x2 Systolic Array with UVM Testbench

   SystemVerilog 1

3. async_fifo async_fifo Public

   Asynchronous FIFO RTL and verification project featuring CDC-safe Gray-code pointers, SystemVerilog/UVM, SVA, functional coverage, and formal verification.