reorder-buffer

A cycle-accurate out-of-order RISC-V processor simulator in C++, implementing Tomasulo's algorithm with a Reorder Buffer (ROB), Reservation Stations, a Load/Store Queue, and a dynamic branch predictor.

Out-of-order processor pipeline simulator with configurable ROB, IQ, and dispatch width

Un simulador moderno para aprender arquitectura de computadores. Tiene editor con resaltado de sintaxis, cronograma interactivo del pipeline, registros y memoria en tiempo real, y soporte para instrucciones enteras, de punto flotante y vectoriales.

Superscalar CPU simulation models how modern processors execute instructions in parallel and manage hazards, analyzing and scheduling Python function instructions using advanced CPU features.