This repository provides a parameterized hardware implementation of a Posit Arithmetic Unit (PAU) written in Verilog. It supports addition, subtraction, multiplication, and division over configurable posit formats, and includes a full verification framework using a C++ golden reference model.
fpga rtl verilog systemverilog hdl posit posit-arithmetic hardware-accelerator hardware-design universal-number floating-point-alternative machine-learning-accelerator
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Updated
Jul 25, 2025 - Verilog