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andrea-cpu96 / vhdl-cookbook

A github page with common VHDL templates, ready to be copied and used in your projects.

asic fpga simulation electronics vhdl rtl finite-state-machine hdl testbench digital-design code-snippets hardware-description-language fpga-development vhdl-examples fpga-programming vhdl-templates

Updated Sep 11, 2026
HTML

sdnellen / open-register-design-tool

Star

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design

Updated Jun 25, 2026
Verilog

firesim / aws-fpga-firesim

Star

AWS Shell for FireSim

fpga aws-ec2 fpga-development aws-fpga

Updated Nov 13, 2024
VHDL

atmarachchige0081 / Tang-FPGA-Studio

Star

Beginner-friendly open-source FPGA IDE for Sipeed Tang Nano and Tang Primer: Verilog/SystemVerilog, simulation, waveforms, synthesis, JTAG, flash, and UART.

Updated Oct 4, 2026
Rust

arnav-gudibande / fpga-intro-guide

Star

Introductory guide to building and programming FPGAs

fpga hdl modelsim quartus-prime quartus fpga-development

Updated Aug 3, 2017
Tcl

vicharak-in / zen

Star

ZEN : A feature full FPGA Dev board that does not break your bank.

fpga micropython verilog circuitpython hdl fpga-soc verilog-hdl fpga-board fpga-development fpga-programming micropython-rpi-pico rp2350 rp2350b rp2350-pizero rp2350-project

Updated Sep 16, 2026
Verilog

zhangym0115 / Vflux

Star

A lightweight graphical FPGA development workflow tool built around OSS CAD Suite.

fpga desktop-application icestorm yosys ice40 fpga-development verilog-project nextpnr nextpnr-ice40 nextpnr-ecp5 icesugar oss-cad-suite

Updated May 8, 2026
JavaScript

alexeykosinov / UT8QNF8M8-Controller

Star

UT8QNF8M8 NOR Flash Controller VHDL Module

vhdl fpga-firmware fpga-development aeroflex ut8qnf8m8 nor-flash

Updated Jan 14, 2019
VHDL

Strato75 / FPGACorrelator

Star

FPGA backend correlator for the microwave holography system installed on the Sardinia Radio Telescope (SRT)

python fpga backend verilog srt radioastronomy sardinia fpga-development correlator sardinia-radio-telescope microwave-holography

Updated Mar 26, 2020
Verilog

Verilog-based vending machine controller IP core, supporting multi-clock domain operation, inventory management, and currency denominations. Built with the APB protocol for efficient configuration, it offers smart change calculation and robust error handling. Developed in the SURE ProEd internship training with experts.

embedded-systems error-handling verilog memory-management vlsi digital-systems fpga-development vlsi-design hardware-design internship-project apb-protocol sure-trust vending-machine-controller sure-proed multi-clock-domain

Updated Apr 25, 2025
Verilog

Angelo-EEE / FPGA-UART-Loopback--VHDL

Star

A complete VHDL UART transceiver and loopback interface featuring 2-stage input synchronization, mid-bit oversampling, framing error detection, and an integrated FIFO buffer.

fpga vhdl uart testbenches fpga-soc testbench uart-protocol fpgas uart-interface fpga-board vhdl-code fpga-development uart-tx vhdl-examples uart-transmitter uart-receiver fpga-programming uart-communication testbench-verification

Updated Sep 17, 2026
VHDL

accemic / abc-flow

Star

Text-based dependency files for FPGA projects.

hdl fpga-development

Updated Jun 11, 2026
Shell

AZsnake / sensor-test-framework-soft-core

Star

VU13P FPGA MIPI CSI-2 验证框架（MicroBlaze）：Vivado BD + Vitis 固件 + PySide6，2-Lane RAW10（IMX298）

Updated Jun 26, 2026
Python

panktipatel1711 / VLSI-Digital-Clock-Alarm

Star

A parameterizable and synthesizable single-clock-domain Digital Clock core with integrated Alarm, Snooze, and 12/24-hour display modes implemented in Verilog HDL. Features double-register button debouncing and a time-multiplexed 7-segment display driver.

verilog systemverilog testbench digital-clock digital-design hardware-description-language fpga-development vlsi-design rtl-design fsm-controller

Updated Jun 21, 2026
Verilog

Prateek2174 / tang_primer_human_cnn

Star

A from-scratch CNN running entirely in Verilog on a Tang Primer 20K (Gowin GW2A-18C), classifying whether a person is present in a scene.

fpga cnn verilog cnn-keras cnn-model fpga-accelerator cnn-architecture fpga-board cnn-for-visual-recognition fpga-development cnn-classification verilog-project fpga-programming verilog-code

Updated Sep 4, 2026
Verilog

AZsnake / sensor-test-framework-s2c

Star

S2C VP1902 FPGA MIPI CSI-2 验证框架（纯 RTL）：Versal PDI + PPro-RT8 + PySide6，2-Lane RAW10（IMX298）

Updated Jul 6, 2026
Verilog

TalhaLand / Verilog-ModelSim-Practices

Star

fpga verilog modelsim fpga-soc fpga-board fpga-development fpga-programming

Updated Aug 8, 2026
Verilog

oluwaferanmi-arowoshola / microblaze-embedded-system

Star

MicroBlaze FPGA embedded system on Nexys DDR using Vivado/Vitis, AXI GPIO peripherals, UART, and C firmware for memory-mapped switch-to-LED hardware control.

c fpga embedded-systems xilinx vivado uart xilinx-fpga digital-design embedded-c microblaze fpga-development vitis memory-mapped-io hardware-software-integration soft-core-processor board-validation axi-gpio nexys-ddr

Updated May 16, 2026
C

AZsnake / sensor-test-framework-pure-rtl

Star

VU13P FPGA MIPI CSI-2 验证框架（纯 RTL）：Vivado BD + mipi_sys_ctrl + PySide6，2-Lane RAW10（IMX298）

python fpga camera rtl verilog xilinx vivado uart hardware-testing fpga-development mipi csi-2 pyside6 bring-up sensor-validation xilinx-ultrascale imx298 vu13p sensor-test-framework

Updated Jun 26, 2026
Verilog

AZsnake / adda-test-framework

Star

VU13P FPGA ADDA 调试与验证框架：UART/SPI boot、ADC IQ DSP、DAC 2× DDR、PySide6（SI5340 / AD9640 / AD9117）

Updated Jun 26, 2026
Verilog

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fpga-development

Here are 27 public repositories matching this topic...

andrea-cpu96 / vhdl-cookbook

sdnellen / open-register-design-tool

firesim / aws-fpga-firesim

atmarachchige0081 / Tang-FPGA-Studio

arnav-gudibande / fpga-intro-guide

vicharak-in / zen

zhangym0115 / Vflux

alexeykosinov / UT8QNF8M8-Controller

Strato75 / FPGACorrelator

Preven-K / Vending-Machine

Angelo-EEE / FPGA-UART-Loopback--VHDL

accemic / abc-flow

AZsnake / sensor-test-framework-soft-core

panktipatel1711 / VLSI-Digital-Clock-Alarm

Prateek2174 / tang_primer_human_cnn

AZsnake / sensor-test-framework-s2c

TalhaLand / Verilog-ModelSim-Practices

oluwaferanmi-arowoshola / microblaze-embedded-system

AZsnake / sensor-test-framework-pure-rtl

AZsnake / adda-test-framework

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