I am an Electronics and Communication Engineering graduate specializing exclusively in ASIC/SoC Design Verification. My focus centers on functional verification, testbench architecture, and ensuring silicon designs meet specification before fabrication.

• Hardware Description: SystemVerilog, Verilog
• Verification Methodologies: UVM, Constrained Randomization, Functional Coverage, SVA
• EDA Tools: Cadence Virtuoso, EDA Playground
• Core Competencies: Digital Logic (FSMs, Microprocessor Architectures), Protocol Verification, Testbench Architecture

I am currently transitioning foundational digital design concepts into industry-standard verification IP. My immediate focus is mastering advanced SystemVerilog and UVM methodologies to architect and verify complex silicon for semiconductor leaders.

📫 Let's Connect: https://www.linkedin.com/in/damisettytapan/