Raise SIGBUS for an unaligned lock cmpxchg8b - #2816

On aarch64, lock cmpxchg8b on an address that isn't 8-byte aligned branches to segfault_write. That exit reports tlb->segfault_addr, but nothing on this path sets it, so the fault carries whatever address is left over:

• If that address is mapped, the page-fault handler has nothing to do and the instruction retries forever, at 100% CPU.
• If it isn't, the guest gets a SIGSEGV for an unrelated address.

Python 3.14, which Alpine 3.24 ships, hits this at startup and does either one, depending on what was left there.

As discussed in #2813, this raises SIGBUS instead, with BUS_ADRALN and the operand's address. The x86_64 host's gadget uses the host's own lock cmpxchg8b and is unchanged.

Tested on an arm64 Mac with the Alpine 3.24 x86 rootfs:

• An unaligned __atomic_fetch_add on a uint64_t gets SIGBUS, with si_code 1 and si_addr at the operand.
• The aligned case is unaffected.
• python3 now exits with "Bus error" instead of hanging or segfaulting.

🤖 Generated with Claude Code