STM32H5: ADC circular GPDMA so battery/current track live values - #15419
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WalkthroughSTM32H5 ADC initialization now stores per-device GPDMA nodes and queues, builds an ADC-to-buffer transfer node, enables circular linked-list mode, and attaches the queue through the HAL linked-list APIs. ChangesSTM32H5 ADC DMA
Estimated code review effort: 3 (Moderate) | ~20 minutes Possibly related PRs
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@coderabbitai full review - for reference see also datasheet and reference manual |
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On STM32H5 the ADC DMA channel was configured as a one-shot linear transfer (DMA_NORMAL). H5's GPDMA has no plain circular mode, so HAL_ADC_Start_DMA() took its one-shot branch and transferred a single scan: the conversion buffer was filled once at boot and then frozen forever, so VBAT/current/RSSI never tracked the real inputs. Rebuild the ADC DMA as a circular linked-list queue (HAL_DMAEx_List_* with DMA_LINKEDLIST_CIRCULAR, one static node/queue per ADC device) so HAL_ADC_Start_DMA() takes the linked-list branch and continuously refreshes the buffer. The conversion buffer (destination) is allocated to GPDMA master PORT1: both ports reach all memories on H5, PORT1 just has the zero-latency fast bus multiplexer to SRAM (RM0481 fig. 1), matching the DShot/WS2811 port allocation.
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…aflight#15419) fix(STM32H5): ADC circular GPDMA so battery/current track live values On STM32H5 the ADC DMA channel was configured as a one-shot linear transfer (DMA_NORMAL). H5's GPDMA has no plain circular mode, so HAL_ADC_Start_DMA() took its one-shot branch and transferred a single scan: the conversion buffer was filled once at boot and then frozen forever, so VBAT/current/RSSI never tracked the real inputs. Rebuild the ADC DMA as a circular linked-list queue (HAL_DMAEx_List_* with DMA_LINKEDLIST_CIRCULAR, one static node/queue per ADC device) so HAL_ADC_Start_DMA() takes the linked-list branch and continuously refreshes the buffer. The conversion buffer (destination) is allocated to GPDMA master PORT1: both ports reach all memories on H5, PORT1 just has the zero-latency fast bus multiplexer to SRAM (RM0481 fig. 1), matching the DShot/WS2811 port allocation.
Scope change: the WS2811 LED-strip fix has been split out to #15438 — a deep review against RM0481 found an additional bug there (TIM handle state latch-up freezing the strip after the first frame) that needs an on-hardware retest, while this ADC fix is already hardware-verified. This PR now carries only the ADC change. A comment-only follow-up for the DShot driver's GPDMA rationale is #15439.
On STM32H5 the ADC DMA channel was configured as a one-shot linear transfer (
DMA_NORMAL). H5's GPDMA has no plain circular mode, soHAL_ADC_Start_DMA()took its one-shot branch and transferred a single scan: the conversion buffer was filled once at boot and then frozen forever, so VBAT/current/RSSI never tracked the real inputs.Rebuild the ADC DMA as a circular linked-list queue (
HAL_DMAEx_List_*withDMA_LINKEDLIST_CIRCULAR, one static node/queue per ADC device) soHAL_ADC_Start_DMA()takes the linked-list branch and continuously refreshes the buffer.The conversion buffer (destination) is allocated to GPDMA master PORT1. Note the rationale was corrected during review: both GPDMA master ports reach all memories on H5 (RM0481 §2.1.5, fig. 1) — PORT1 simply has the zero-latency fast bus multiplexer to SRAM, matching the DShot/WS2811 port allocation. The linked-list construction was verified against the vendored H5 HAL:
HAL_ADC_Start_DMA()overwrites the head node's source/destination/length (converting samples to bytes itself), and the circular CLLR update mask refetches CTR1/CTR2/CBR1/CSAR/CDAR on every loop, so the buffer genuinely refreshes each scan.Verified working on hardware: VBAT/current/RSSI track live values.
make STM32H563builds clean with zero warnings.