Popular repositories Loading

1. SILICLUSTER_UART_TX_and_UART_RX_2025 SILICLUSTER_UART_TX_and_UART_RX_2025 Public

   Verilog implementation of UART Transmitter and Receiver modules designed for Silicluster 2025 using SkyWater 130 nm PDK. Includes RTL design, functional testbenches, OpenLane-generated GDS layouts,…

   Verilog 1

2. Assignment1_XOR Assignment1_XOR Public

   Python

3. Assignment2_Interface Assignment2_Interface Public

   Verilog

4. NASSCOM_SEMICONDUCTOR_WORKSHOP-July-4-to-13-2025 NASSCOM_SEMICONDUCTOR_WORKSHOP-July-4-to-13-2025 Public

5. ARM32_BIT_CPU_DESIGN ARM32_BIT_CPU_DESIGN Public

   Replicated and implemented a 32-bit ARM-style CPU in Verilog/SystemVerilog, covering full datapath, control logic, ALU, and memory integration, with functional verification through RTL simulation.

   SystemVerilog

6. APB-MEMORY-UVM-VERIFICATION APB-MEMORY-UVM-VERIFICATION Public

   APB Memory Verification using UVM with protocol checks and waveform analysis

   SystemVerilog