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XiangShan

Open-source high-performance RISC-V processor

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  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 7.3k 956

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 445 152

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 101 40

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 187 110

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 73 76

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 352 146

Repositories

Showing 10 of 109 repositories
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU's past year of commit activity
    C 352 146 40 46 Updated Oct 8, 2026
  • difftest Public

    Modern co-simulation framework for RISC-V CPUs

    OpenXiangShan/difftest's past year of commit activity
    C++ 187 MulanPSL-2.0 110 8 16 Updated Oct 8, 2026
  • OpenXiangShan/XiangShan-Dashboard's past year of commit activity
    Vue 2 0 0 1 Updated Oct 8, 2026
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan's past year of commit activity
    Scala 7,295 MulanPSL-2.0 956 145 174 Updated Oct 8, 2026
  • YunSuan Public

    This repo includes XiangShan's function units

    OpenXiangShan/YunSuan's past year of commit activity
    Scala 35 MulanPSL-2.0 21 3 2 Updated Oct 8, 2026
  • XSAI Public Forked from OpenXiangShan/XiangShan

    A fork of Xiangshan for AI

    OpenXiangShan/XSAI's past year of commit activity
    Scala 59 MulanPSL-2.0 982 4 3 Updated Oct 8, 2026
  • XSAICache Public Forked from OpenXiangShan/XSCache

    A fork of XSCache for XSAI. Supports High-Bandwidth L2 Cache design.

    OpenXiangShan/XSAICache's past year of commit activity
    Scala 1 8 0 1 Updated Oct 8, 2026
  • gsim Public
    OpenXiangShan/gsim's past year of commit activity
    C++ 86 13 2 9 Updated Oct 8, 2026
  • XiangShanLab Public

    XiangShanLab is the open-source XiangShan ecosystem's entry layer — a learning, practice, and collaboration hub spanning the RISC-V processor core and its specialized domains, making high-performance processor design learnable, doable, and participable, and welcoming collaborators from academia and industry to join real open-source development.

    OpenXiangShan/XiangShanLab's past year of commit activity
    Scala 44 24 52 2 Updated Oct 8, 2026
  • GEM5 Public
    OpenXiangShan/GEM5's past year of commit activity
    C++ 161 BSD-3-Clause 94 18 102 Updated Oct 8, 2026