FPMIX

Copyright 2026 Politecnico di Milano.
Authors: Andrea Galimberti, Davide Zoni.
Contacts: andrea.galimberti@polimi.it, davide.zoni@polimi.it.
Date: May 5, 2026.

Floating-point unit (FPU) with design-time configurable floating-point (FP) formats for each operation type and supporting any FP format with length up to the width of the integer format.
Design-time configurable parameters include the FP format's mantissa widths of each operation type, namely:

• addition/subtraction,
• multiplication,
• division,
• FP-to-int conversions,
• int-to-FP conversions,
• comparisons.

Other design-time configurable parameters are the FP format's exponent width, the integer format's width and the approximation and precision of the Goldschmidt divider.

Two SystemVerilog testbenches are provided for validation of the FPU against a DPI C model and for a simpler simulation requiring no support for DPI C, respectively.

FPMIX/
├── pkg/                  # SystemVerilog packages with parameters and helper functions
│   └── fpmix_pkg.sv      # Main package file: configurable parameters at lines 8-52
├── rtl/                  # SystemVerilog modules for FPMIX FPU design
│   ├── fpmix_top.sv      # Top module
│   └── ...
├── tb/
│   ├── dpi_fpmix.c       # Reference model for DPI-C verification
│   ├── tb_fpmix.sv       # SystemVerilog testbench for simple simulation
│   └── validate_fpmix.sv # SystemVerilog testbench for verification against DPI C model
├── scripts/              # Non-project-mode flow for Vivado synth., impl. and sim.
|   └── ...
└── xdc/
    └── timing.xdc        # Clock constraints for implementation on VCU118 and Artix-7 100

Vivado Version: 2024.2
Synthesis: Default strategy, -mode out_of_context
Implementation: Default strategy, Post-Route Physical Optimization (phys_opt_design) enabled

Virtex UltraScale+ VCU118 Evaluation Platform - FPGA: xcvu9p-flga2104-2L-e

Artix-7 100 - FPGA: xc7a100tcsg324-1

Utilization Breakdown

Target: Artix-7 100 (xc7a100tcsg324-1) FPGA
Clock: 85MHz

Operations Latency

The design includes a simple tb_fpmix testbench contained in the tb/tb_fpmix.sv file.
Simulations were run in Vivado 2024.2 (GUI project mode, tested on Ubuntu 22.04.5 and Windows 11 25H2).

The design includes a SystemVerilog DPI-C model (tb/dpi_fpmix.c), used by the validate_fpmix testbench contained in the tb/validate_fpmix.sv file. To run simulations with DPI enabled, follow these steps:

1. Compile the DPI library using XSim C compiler (xsc)
   From the Vivado Tcl Console, run:

   exec xsc <pathToDPIFile>/dpi_fpmix.c -o <pathToDPIFile>/dpi_fpmix.so

2. Tell XSim to load the DPI shared library during elaboration
   Go to: Flow Navigator → Project Settings → Simulation → Elaboration options and add the following flag in xsim.elaborate.xelab.more_options:

   --sv_lib dpi_fpmix
   

3. Place the shared object in the XSim working directory
   Copy the compiled .so file into:

   <VivadoProject>/<projectName>.sim/sim_1/behav/xsim/
   

   For post-synthesis and post-implementation simulations, copy the .so into the corresponding simulation subdirectories as well.

4. Run simulation as usual
   Use: Flow Navigator → Run Simulation → Run Behavioral Simulation

   For post-synthesis and post-implementation simulations, accordingly use the corresponding actions from the dropdown menu.

Vivado 2024.2, Ubuntu 22.04 shell/Makefile flows (no project).

source <pathToVivadoInstallation>/Xilinx/Vivado/2024.2/settings64.sh # Adjust path
make clean all # Synth/impl/RTL sim/post-synth (VCU118)

Inputs

Outputs