Aurora

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1. OpenRAM OpenRAM Public

   Forked from VLSIDA/OpenRAM

   An open-source static random access memory (SRAM) compiler

   Python

2. constellation constellation Public

   Forked from ucb-bar/constellation

   A Chisel RTL generator for network-on-chip interconnects

   Scala

3. OpenROAD-flow-scripts OpenROAD-flow-scripts Public

   Forked from The-OpenROAD-Project/OpenROAD-flow-scripts

   OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

   Verilog

4. lisnoc lisnoc Public

   Forked from TUM-LIS/lisnoc

   LIS Network-on-Chip Implementation

   Verilog

5. chisel chisel Public

   Forked from chipsalliance/chisel

   Chisel: A Modern Hardware Design Language

   Scala

6. chipyard chipyard Public

   Forked from ucb-bar/chipyard

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   Scala