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Set the U-mode implemented bit to MISA.
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‎src/csr.rs‎

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Original file line numberDiff line numberDiff line change
@@ -189,6 +189,7 @@ impl State {
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pub fn new() -> Self {
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let mut csrs = [0; CSR_SIZE];
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let misa: u64 = (2 << 62) | // MXL[1:0]=2 (XLEN is 64)
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(1 << 20) | // Extensions[20] (User mode implemented)
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(1 << 18) | // Extensions[18] (Supervisor mode implemented)
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(1 << 12) | // Extensions[12] (Integer Multiply/Divide extension)
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(1 << 8) | // Extensions[8] (RV32I/64I/128I base ISA)

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